The present invention relates to a high-frequency switch circuit, and more particularly, to a high-frequency switch circuit having field-effect transistors.
There has been known a multi-port high-frequency switch circuit for switching connections between an antenna terminal and multi-port terminals of a multimode/multiband wireless communication device such as Global System for Mobile Communications (GSM) or Universal Mobile Telecommunications System (UMTS). Such a high-frequency switch circuit is required to be low in insertion loss and maintain linearity of an output signal even when a large signal is supplied. In general, as the high-frequency switch circuit that satisfies these performance requirements, a high-frequency switch circuit having field-effect transistors (hereinafter, FETs) formed by using GaAs has been used.
Meanwhile, in recent years, a metal-oxide-semiconductor field-effect transistor (hereinafter, MOSFET) formed by using Si has been proposed (refer to Japanese Unexamined Patent Application Publication No. 2009-194891). The use of the MOSFET greatly reduces a parasitic capacitance of a device and improves an insertion loss property of a switch, with the introduction of a Silicon-On-Insulator (SOI) technology. In this method, a plurality of MOSFETs are connected in series and in multistage, thereby preventing a malfunction when a large signal is supplied, and improving withstand voltage. However, the configuration in which the plurality of MOSFETs are connected in series and in multistage generates a second harmonic wave and a third harmonic wave.
FIG. 9 is a circuit diagram of a Single Pole Double Throw (SPDT) switch. Note that the actual multi-port high-frequency switch circuit is designed for multi-port switching, such as a Single Pole 4 Throw (SP4T) and an SP10T. However, the SPDT switch is described to simplify the explanation in this specification. In the SPDT switch shown in FIG. 9, a plurality of FETs (T111 to T114) are connected in series between an antenna terminal (an ANT terminal) and a port 1 terminal. Further, a plurality of FETs (T121 to T124) are connected in series between the ANT terminal and a port 2 terminal. Gates of the FETs (T111 to T114) that are connected between the ANT terminal and the port 1 terminal are connected to each other via resistor elements and supplied with a common control signal 131. Similarly, gates of the FETs (T121 to T124) that are connected between the ANT terminal and the port 2 terminal are connected to each other via resistor elements and supplied with a common control signal 132.
In general, a selector switch selects a conduction of one of the plurality of ports. Therefore, the FETs (T121 to T124) that are connected between the ANT terminal and the port 2 terminal become off-state when the FETs (T111 to T114) that are connected between the ANT terminal and the port 1 terminal become on-state, for example. On the other hand, the FETs (T111 to T114) that are connected between the ANT terminal and the port 1 terminal become off-state when the FETs (T121 to T124) that are connected between the ANT terminal and the port 2 terminal become on-state.
FIG. 10 is a cross-sectional view showing a structure of the FET used for such a switch (refer to Japanese Unexamined Patent Application Publication No. 2009-194891). The FET shown in FIG. 10 is formed by using the SOI technology. The FET shown in FIG. 10 includes a Si substrate 112, an embedded oxide film layer 113 formed on the Si substrate 112, a body region (an SOI layer) 116 formed on the embedded oxide film layer 113, a source region 121, a drain region 122, a gate oxide film 115 formed on the body region 116, and a gate electrode 123 formed on the gate oxide film 115. The FETs are separated by element isolation layers 114. In general, the high-frequency switch circuit is designed so as to be symmetrical to an input and an output. Therefore, the FET shown in FIG. 10 has the structure in which the source region 121 and the drain region 122 are symmetrical to the center of the gate electrode 123 and the body region 116.
In the high-frequency switch circuit, as shown in FIG. 10, the FET is generally configured to have a large gate width so as to reduce the on resistance of the conducting port. Therefore, a multi-finger type FET in which the gate electrode 123, the drain region 122, and the source region 121 are arranged as shown in FIG. 11 is widely used. The multi-finger type FET shown in FIG. 11 forms an FET by connecting a plurality of unit devices in parallel.
In addition, Japanese Unexamined Patent Application Publication No. 2007-073815 discloses a semiconductor device that can improve distortion characteristics. The semiconductor device disclosed in this document is used for a high-frequency switch circuit in which a high frequency signal via either a source electrode or a drain electrode in a multi-gate FET is input or output via the other electrode, and passing or blocking of the high frequency signal is controlled by the electric potentials of control terminals connected to multiple gate electrodes. In this technique, the length of a source side pent roof in a first gate nearest to the source electrode and the length of a drain side pent roof in a third gate nearest to the drain electrode are longer than that of the other pent roof in the gate electrode and they constitute an additional capacity.
In addition, Japanese Unexamined Patent Application Publication No. 2008-263523 discloses a technique in which a second-order harmonic distortion of a high frequency signal transmitted via a high-frequency switch circuit is reduced. In the high-frequency switch circuit disclosed in this document, FETs constituting a receiving side transfer circuit is constituted as a serial structure at odd-numbered stages. Each FET stage is constituted of a parallel body of MOSFETs where positions of a source electrode and a drain electrode are exchanged and the gate width of each of the MOSFETs is reduced to a half in comparison with the case of constituting the receiving side transfer circuit of one line of MOSFETs.
In addition, Japanese Unexamined Patent Application Publication No. 2008-181911 discloses a semiconductor device in which linearity is secured when turning on the semiconductor device, and deterioration in breaking characteristics is suppressed when turning off the semiconductor device. The semiconductor device disclosed in this document has a plurality of terminals and a switch having a plurality of FETs connected among the plurality of terminals. The gate width of first FETs connected to at least one of the plurality of terminals of the plurality of FETs is larger than the gate width of second FETs connected to the subsequent stage of the first FETs of the plurality of FETs. A sum of length of a source electrode and a drain electrode of the first FETs in a direction perpendicular to the gate width of the first FETs is smaller than a sum of length of a source electrode and a drain electrode of the second FETs in a direction perpendicular to the gate width of the second FETs.